Tuesday, January 27, 2004

I have recently helped two senior candidates get hired through a recruiter who is one of the most effective recruiters I have ever dealt with. He has positions in both Austin Texas and Silicon Valley. The positions are as follows:

If you have the skills and interest I advise you to contact me in order to discuss. The recruiter works directly with the hiring managers and will get you an interview very quickly if you have the right background.

1) Sr Memory Controller Logic/Microarchitecture Engineer, Silicon Valley, CA,
resp for architectural and micro-architectural design of an integrated DRAM memory controller for high end processor. 7-10 yrs exp. has lead technical projects in microprocessor design. Familiar with DDR and DDR2 specs, verilog knowledge. Open on title and salary. Looking for a Memory Controller guru.

2) Sr ASIC Design Engineer/Manager, Silicon Valley, Ca.
Lead 4-5 engineers, Has to be an ASIC expert, 7-10 yrs experience. Must know back end flow (physical design), front end flow and DFT issues.

3) Sr Circuit Implementation Engineer, Silicon Valley, Ca, Experience with back end flow of ASIC Design (Physical Design),

knowledge of CTS routing tool a plus.

4) Sr Custom Circuit Designers, Silicon Valley, CA.
5 plus years experience in Memory (SRAMS, Caches, TLB's, register files or datapath design)

5) Sr CAD Tool Developer, Silicon Valley, Ca,
Candidate must have strong CAD Tool S/W skills in electrical analysis, solving linear equations, static or spice like tools, crosstalk analysis, electrical rule checking. Must be a C/C++ programmer.

6) Sr CAD Tool Developer, Silicon Valley, Ca,
Place and Route Tool Development, C++ is a requirement, strong S/W development skills, focus is on placement (layout databases, data structures for layout and placement algorithms)

7) Sr CAD Tool Developer, Silicon Valley, Ca,
Expert timing tool developer, static timing analysis, delay calculation, path tracing, characterization. Understands signal integrity, knows prime time a plus. C/C++ a must.

8) Sr Software Optimization Engineer, Silicon Valley, CA,
A solid software candidate to work in a CAD tool environment. Strong algorithmic approach, BS/MS CS, Solid C++ programming skills, knows geometric optimization, linear programming, graph algorithms, algorithms for optimization, knowledge of whole optimization domain.

9) I/O and PLL Design Engineers, Austin, TX
4+ years design experience in high speed I/O and/or PLL design. Leading edge Full Custom Circuit Design experience, BS/MS EE/CS

10) Director of CPU Design, Silicon Valley, CA,
Technical management of mid to large CPU design teams. Could be more on the Circuit side of a project but has to have knowledge of leading a team from architecture to tape out. BS/MS EE/CS, 10+ years experience in Full Custom design and Design Management to lead a next generation high end processor project.

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