Thursday, August 26, 2004

Great Positions Available

Senior ASIC Verification Engineer - 8+ years. Should be very good with writing scripts in perl, C. Should be familiar with SONET, Ethernet, QoS, TCP/IP, ATM, etc. (Silicon Valley)

Senior ASIC Design Engineer - 5+ years. Must have designed multi-million gate ICs for high-speed networking applications. Some FPGA experience is an asset. (Silicon Valley)

Senior Analog Design Manager - 10+ years experience, 5 in management role. Requires experience designing power management ICs such as DC-DC, switching regulators, etc. (Silicon Valley)

Analog Design Engineer - MSEE + 3 years or PhDEE - looking for strong fundamental analog design skills. Experience designing data converters would be an asset. (Boston)

RFIC Design Engineer - MSEE + 5 years - must have experience designing state-of-the-art high speed circuits. (Texas)

Senior Systems Engineer - MSEE (Ph.D. preferred) in signal processing/communications theory. Minimum five years experience in algorithm definition, communication system simulation, and signal processing. (Southern California)

Please contact me for more detail.

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