CPU RTL & Microarchitecture Engineer
RTL design and microarchitecture definition of high-performance microprocessors going into industry leading AI/ML architecture. This senior person coming into this role will define new features and code the RTL across multiple areas of our processor Core. The work is done alongside with a group of highly experienced engineers across various domains of the AI chip.
Responsibilities
- Define architecture and logic design requirements by understanding rapidly evolving AI/ML models; work with engineers across domains to understand real world use cases
- RTL coding in Verilog leveraging on both industry tools as well as open-source infrastructure
- Drive trade-offs for your logic by working closely with performance, DV and physical design engineers to craft optimal solutions that meet the design goals
- Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL and evaluate synthesis, timing and power results
- Debug RTL/logic issues across various hierarchies (ex: core, chip) in both pre-silicon and post-silicon environment
Experience & Qualifications
- BS/MS/PhD in EE/ECE/CE/CS with at least 8 years of experience
- Experience with computer architecture/system components/network/fabrics as a part of a CPU, ASIC or SOC design team
- Expertise in logic design and ability to evaluate functional, performance, timing and power for you design
- Strong experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
- Expertise in microarchitecture definition and specification development
- Prior experience in industry standard ISAs – ARM, RISC-V, X86 preferred
- Strong problem solving and debug skills across various levels of design hierarchies