Principal IO Design Architect, HBM

Responsibilities will include, but are not limited to: Design low-power high-speed Tx, Rx, clock tree Analyze timing jitter and variation to improve speed and optimize design Contribute to cross group communication to work towards standardization and group success Experience with circuit verification and optimization including layout verification and parasitic extractions of the circuits Minimum 5+ years of proven experience in the Memory industry with an MS EE degree, or 7+ years with a BS EE or equivalent experience.