This SkyWater Device Modeling Principal Engineer will primarily lead device characterization, perform compact model extraction, and contribute to device design for advanced CMOS-based technologies.
Responsibilities:
- New device development, transfer, and integration in a manufacturing environment.
- Liaison with Design Enablement group on matters relating device design, and PDK development for CMOS-compatible technologies as needed to support SkyWater foundry technologies.
- Device characterization, extraction and validation of SPICE-compatible models
- Test chip design, layout and characterization as required to support the above technology developments.
- Serve as a subject matter expert to customers and SkyWater colleagues for platform technology elements, model constraints, and new device process targeting.
Minimum Qualifications:
- MS/PhD in Engineering, Physics, or related field.
- Relevant combination of advanced degree and/or years of experience.
- Expertise in device characterization, simulation, and validation of SPICE-compatible models from silicon, using tools such as Spectre, IC-CAP, MBP, and Verilog.
- Understanding of general performance, optimization, and yield limiters relevant to deep-submicron field effect transistors and related CMOS-compatible technologies.
- Programming background, especially python, with familiarity in automation for analysis of large datasets.
- Ability to interact with both internal and external customers.
- Clear problem-solving capability, data driven, inventive solution oriented and can articulate thought processes.
- Can work both independently and in cross-functional teams for problem solving.
- US Citizenship Required: This position will require the holding of or ability to obtain government security clearance which requires U.S Citizenship.
Preferred Qualifications:
- 6+ years of advanced device development or modeling experience.
- Background in device development and integration in some or all of the following fields: CMOS, MEMS, photonics, and superconducting.
- Experience with model validation and device layout in a Cadence environment.
- Background in physics-based device simulation, design, and characterization for topics such as PEX, TCAD, noise, ESD, and stress effects.
- Experience in DOE and CMOS device design for extreme environments such as cryogenic, radiation, or high temperature.
- Knowledge of DOE, SPC, and 6-sigma concepts and applications.
- Familiarity with typical mixed-signal IC design.
- Experience in project technology transfers into or out of a semiconductor foundry.